1. Field of the Invention
This invention relates to semiconductor device manufacturing, and more particularly, to an improved oxide-nitride layer and a method for making the same.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
The formation of oxide layers upon silicon layers is commonly used within fabrication processes of a variety of semiconductor devices. Sometimes, however, irregularities may exist within the silicon surface or may be created during the formation of the oxide layer, both of which may bring about a disjointed oxide pattern which can lead to dangling bonds, often referred to as “interface traps” at the oxide-silicon interface. Dangling bonds are generally sporadic silicon-to-oxide atomic bonds, which readily accept mobile carriers (electrons or holes) at the oxide-silicon interface. The build-up of mobile carriers may generate high electric fields across the oxide layer and the continual passage of charge across the tunnel oxide region of a device. Consequently, interface traps may cause a variety of problems, such as shifts in the threshold voltage (Vt) of an ensuing device and/or breakdown of the oxide layer. In addition, the build-up of mobile carriers may increase the back tunneling current of non-volatile semiconductor memory cells, thereby dissipating the memory of the cells more quickly. Consequently, the presence of interface traps may degrade the long-term retention of non-volatile memory cells.
In some cases, interface traps within fabricated devices may be passivated such that the build-up of mobile carriers are reduced or eliminated for an amount of time, thereby theoretically improving device reliability. In particular, the silicon-to-oxide atomic bonds within an oxide-silicon interface may be made stronger to withstand the operation of the device for a longer period of time. For example, in some cases, devices may be annealed in hydrogen (H2) to passivate interface traps. In other embodiments, devices may be annealed in deuterium (D2) to passivate interface traps. Such anneals are typically performed subsequent to the formation of the device, such as after a contact or bond pad etch.
Although using hydrogen or deuterium anneals may passivate interface traps of fabricated devices, using such anneals may present problems affecting the functionality and reliability of the devices. In particular, such anneal processes typically require the use of “pure” hydrogen (H2) or deuterium (D2). “Pure” hydrogen and deuterium may refer to gases, which are free or substantially absent of other elements. Typically, free hydrogen and free deuterium include safety hazards, which make them difficult to incorporate into semiconductor fabrication processes. In particular, free hydrogen and free deuterium are both considered explosion hazards when used at temperatures greater than approximately 500° C. or exposed to oxygen. The temperature required for deuterium anneals, however, is typically between 500° C. and 700° C. Such a high temperature along with an annealing duration between approximately 4 to 5 hours, which is typically required for deuterium anneals, may severely degrade metallization with a device and/or cause certain dielectric materials to reflow. Moreover, such an anneal process may undesirably increase the thermal budget of a fabrication process, degrading the functionality of devices fabricated therefrom. In addition, deuterium cannot diffuse through nitride. Consequently, the use of a deuterium anneal in devices, which include nitride layers, such as SONOS devices, are limited in their capability to improve device reliability.
It would therefore be desirable to develop a safe and non-destructive method for passivating dangling bonds within a lower oxide-silicon interface of a SONOS structure. In particular, it may be desirable to develop a method for diffusing deuterium into a lower oxide-silicon interface of a SONOS structure.